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71M6545/71M6545H Data Sheet
Table 51: SPI Command Sequences
Command Sequence
ADDR 1xxx xxxx STATUS
Byte0 ... ByteN
ADDR 0xxx xxxx STATUS
Byte0 ... ByteN
Description
Read data starting at ADDR. ADDR is auto-incremented until SPI_CSZ
is raised. Upon completion, SPI_CMD ( SFR 0xFD ) is updated to 1xxx xxxx
and an SPI interrupt is generated. The exception is if the command
byte is 1000 0000. In this case, no MPU interrupt is generated and
SPI_CMD is not updated.
Write data starting at ADDR. ADDR is auto-incremented until SPI_CSZ is
raised. Upon completion, SPI_CMD is updated to 0xxx xxxx and an SPI
interrupt is generated. The exception is if the command byte is 0000
0000. In this case, no MPU interrupt is generated and SPI_CMD is not
updated.
Table 52: SPI Registers
Name
EX_SPI
SPI_CMD
SPI_E
IE_SPI
SPI_SAFE
Location
2701[7]
SFR FD[7:0]
270C[4]
SFR F8[7]
270C[3]
Rst
0
–
1
0
0
Wk
0
–
1
0
0
Dir
R/W
R
R/W
R/W
R/W
Description
SPI interrupt enable bit.
SPI command. The 8-bit command from the bus master.
SPI port enable bit. It enables the SPI interface on pins
SPI_DI, SPI_DO, SPI_CSZ and SPI_CKI.
SPI interrupt flag. Set by hardware, cleared by writing a 0.
Limits SPI writes to SPI_CMD and a 16 byte region in
DRAM when set. No other write operations are permitted.
SPI_STAT contains the status results from the previous
SPI transaction
Bit 7 - 71M6545/H ready error: the 71M6545/H was not
ready to read or write as directed by the previous
command.
Bit 6 - Read data parity: This bit is the parity of all bytes
read from the 71M6545/H in the previous command.
Does not include the SPI_STAT byte.
SPI_STAT
2708[7:0]
0
0
R
Bit 5 - Write data parity: This bit is the overall parity of
the bytes written to the 71M6545/H in the previous
command. It includes CMD and ADDR bytes.
Bit 4:2 - Bottom 3 bits of the byte count. Does not
include ADDR and CMD bytes. One, two, and three
byte instructions return 111.
Bit 1 - SPI FLASH mode: This bit is zero when the
TEST pin is zero.
Bit 0 - SPI FLASH mode ready: Used in SPI FLASH
mode. Indicates that the flash is ready to receive
another write instruction.
SPI Flash Mode (SFM)
In normal operation, the SPI slave interface cannot read or write the flash memory. However, the
71M6545/H supports a special flash mode (SFM) which facilitates initial programming of the flash memory.
When the 71M6545/H is in this mode, the SPI can erase, read, and write the flash memory. Other
memory elements such as XRAM and IO RAM are not accessible in this mode. In order to protect the
flash contents, several operations are required before the SFM mode is successfully invoked.
In SFM mode, the 71M6545/H supports n byte reads and dual-byte writes to flash memory. See the SPI
Transaction description on Page 60 for the format of read and write commands. Since the flash write
62
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